As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. The gate runs vertically alongside the vertical fin channel. Thus, with VFETs the gate length (Lg) is decoupled from the device footprint, and as such VFETs have been pursued as a potential device option for scaling CMOS to the 5 nanometer (nm) node and beyond.
For many circuit applications there is a need for devices with different gate lengths (Lg). With a VFET architecture, however, creating different gates lengths can be challenging due to the vertical orientation of the fin channel.
Therefore, techniques for efficiently and effectively forming VFET devices with different gate lengths would be desirable.